1. Field of the Invention
The present invention relates to a microelectronic device, and in particular, to a microelectronic device provided with an integrated circuit core and a boundary scan test interface, which share a number of pre-selected pins.
2. Description of Related Art
In a printed circuit board (PCB) on which a plurality of microelectronic devices such as integrated circuits (ICs) are mounted, an interconnection test is required to assure correct interconnections between respective ICs on the board. For example, the Boundary Scan test which is compliant with IEEE 1149.1 standard A is a typical measure for such an interconnection test.
In general, the microelectronic device includes an IC core for execution of main functions, and a boundary scan test interface for testing. FIG. 1 illustrates an example of a conventional microelectronic device 100, which comprises an IC core 101, a boundary scan test interface architecture for boundary scan tests, and pins dedicated to the architecture. As shown in FIG. 1, the boundary scan test interface includes a test access port (TAP) controller 102, an instruction register 103, a bypass register 104, and boundary scan units 105. In FIG. 1, there are five pins dedicated to the boundary scan test, which are pin TDI, pin TDO, pin TCK, pin TMS, and pin TRST, respectively. In other function modes of the microelectronic device 100, these pins are not to be used. When the boundary scan test mode is performed, the pin TDI is used for inputting serial data, the pin TDO is used for outputting serial data, the pin TMS is used for selecting input, the pin TCK is used for clock input, and the pin TRST is used for resetting the system. Among these pins, the pin TRST is not essential and may be used or removed depending on the design.
Generally, the TAP controller 102 enters the scan test mode based on a signal input from the pin TMS. For example, when the signal input to the pin TMS is 0 (low level), the TAP controller 102 enters the boundary scan test mode. In the boundary scan test mode, the TAP controller 102 controls serial test data to be input from the pin TDI and output to another electronic device via a scan chain formed with a plurality of boundary scan units 105, in order to test whether the interconnection between the microelectronic device 100 and the electronic device is normal. After completing such tests, if the microelectronic device operates in the normal operation mode, the boundary scan test interface does not have to be functional any more and these dedicated pins are then idle. In other words, these pins are redundant in the operation modes other than the boundary scan test mode.
As to functions of the instruction register 103, the bypass register 104, and the boundary scan units 105 in the boundary scan test mode, please refer to the IEEE 1149.1 standard. Detailed explanations are omitted here for the sake of brevity.
The number of pins consumed affects the fabrication cost of IC chips. In other words, the greater the number is, the higher the cost is. Therefore, if the number of pins necessary for an IC chip can be reduced, the fabrication cost can be reduced significantly.